1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor, and more specifically to a structure of a semiconductor device for improving the operation performance of the semiconductor device, and a manufacturing method for obtaining the structure.
2. Description of the Background Art
FIG. 26 shows a circuit diagram of a conventional SOI (Semiconductor On Insulator) type DRAM Dynamic Random Access Memory) cell 100B. A conventional memory cell transistor consists of an n-channel MOS (Metal Oxide Semiconductor) transistor 100. A memory cell capacitor 101 is connected to one end of n-channel MOS transistor 100. A bit line BL is connected to the other end of n-channel MOS transistor 100. The operation of SOI type DRAM cell 100B is such that cell 100B controls a word line WL which is the gate node of n-channel MOS transistor 100, accumulates charges in memory cell capacitor 101 by bit line BL and stores the charges as cell data.
FIG. 27 shows the cross-sectional structure of a DRAM cell 100C which employs an SOI type memory cell transistor. A silicon oxide film (SiO2) is formed on a silicon substrate 1, and a memory transistor is provided on silicon oxide film 2. A pair of n-type impurity regions 4 and 5, between which a p-type body section 3 is put, are provided on the main surface of silicon oxide film 2. A gate electrode 6 of a word line WL node is provided on body section 3 through a gate oxide film 7. A bit line 15 is connected to n-type impurity region 4 through a contact plug 13 which is provided in an interlayer insulating film 14. A memory cell capacitor 12 is connected to n-type impurity region 5 through a contact plug 8 which is provided in interlayer insulating film 14. Memory cell capacitor 12 includes a storage node (lower electrode) 9, a dielectric film 10, and a cell plate (upper electrode) 11.
The parasitic capacitance of the SOI type memory cell transistor is lower than that of an ordinary bulk type memory transistor, the power consumption thereof is lower and the rate thereof is higher since pn junctions are only on the interfaces between p-type body section 3 and n-type impurity regions 4 and 5. Further, because of the barrier effect of silicon oxide film 2, the SOI memory cell transistor is superior to the ordinary bulk type memory transistor in soft error resistance which is an important factor for a memory chip.
However, as shown in FIG. 27, the SOI type memory cell transistor has a so-called floating structure in which body section 3 is not connected to the other nodes, and charges are accumulated in body section 3 by junction leak current on bit line (BL) 15 side and storage node (SN) 9 side. As a result, as shown in FIG. 28, the potential of body section 3 of the SOI type memory cell transistor rises, an increase in channel leak is induced, and the refresh characteristic of the DRAM cell is eventually, disadvantageously deteriorated.
Conventionally, body section 3 has been stabilized by extracting charges by the amplitude of the bit line to regularly decrease (stabilize) the potential of body section 3 (body refresh), or by providing a gate node region (BG) 21 on the rear side of body section 3 (a deeper region than body section 3 of silicon oxide film 2) to decrease the potential of body section 3 as seen in a memory cell transistor employed in a DRAM cell 100D shown in the cross-sectional view of FIG. 29 and the circuit model diagram of FIG. 30.
Nevertheless, the structure of body section 3 remains a floating structure, and the potential of body section 3 increases by junction leak as shown in FIG. 28. Thus, these methods have not been able to essentially solve the disadvantages.